Jobs in Hyderabad

VLSI Design and Verification:(HWD)

Managers Leads Engineers withh 2-16 years of experience.

You have a strong grounding in the fundamentals of VLSI, Processor and Communication design. You have prior experience in micro-architecture definition, design and verification using verilog, System Verilog and/or C++. Senior candidates should have strong grounding in low-power processor micro-architecture, power domain management in RTL, power-aware logic synthesis and physical design, and power analysis.

How to Apply: Send your detailed resume to:careers@ikoa.com including the department code.

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